The present invention relates to techniques of semiconductor devices, and more specifically, to a technique effectively applied to a semiconductor device having a semiconductor chip mounted on a wiring substrate with a plurality of wiring layers stacked thereover.
Japanese Unexamined Patent Publication No. 2010-219498 (Patent Document 1) discloses a semiconductor device having a void or floating pattern formed in a region of a wiring layer opposed to the surroundings of a solder ball and connected to a single wiring.
Japanese Unexamined Patent Publication No. 2002-100932 (Patent Document 2) discloses a semiconductor device in which a cutout portion is provided in a ground pattern to prevent the ground pattern from being superimposed over a wiring pattern for a piezoelectric vibrator including a monitor electrode pad.
Japanese Unexamined Patent Publication No. 2005-340636 (Patent Document 3) discloses a multilayer wiring substrate having a floating conductive layer positioned to be superimposed over ball pads for connecting balls on a surface of the substrate in the thickness direction.